Complementary metal-oxide semiconductors (CMOS) are a major class of integrated circuits (ICs). CMOS chips include microprocessors, microcontrollers, static random access memory (RAM), and other digital logic circuits. An advantage of CMOS technology is that it only uses significant power when its transistors are switching between on and off states. Consequently, CMOS devices use significantly less power and produce less heat than other forms of logic devices. CMOS technology also allows a high density of logic functions on a chip. “Metal-oxide-semiconductor” is a reference to the fabrication of early (and in some cases, the very latest) field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor substrate. Although metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS transistor, current gate electrodes are typically made from polysilicon.
The metal-oxide-semiconductor field-effect transistor (MOSFET) is based on modulation of charge concentration caused by a MOS capacitance. It includes two terminals (source and drain) each connected to separate highly doped regions. These regions can be either p or n-type, with the source and drain regions of the same device having the same polarity. The source and drain (S/D) regions are separated by a doped region of opposite polarity, known as the body. This region is not highly doped. The active region constitutes a MOS capacitance with a third electrode, the gate, which is located above the body and insulated from all of the other regions by an oxide. In current technologies, the gate electrode is further insulated from the S/D regions by one or more dielectric spacers.
In the present and advanced CMOS technologies, there is a need to remove one or more of the dielectric spacers. Applications of the desired structure and method include, but are not limited to, stress engineering for enhanced mobility and integration of advanced gate structures (e.g., finFET, Metal Gate/High-k, etc.). The dielectric spacer can be removed by either a wet chemical etch or by a reactive ion etch (RIE), as known to those skilled in the art. However, there are technology-limiting drawbacks with each methodology. Specifically, lateral etch/undercut which is inherent to wet etch processes at the gate level cannot be tolerated at the pitch used in advanced technologies. Furthermore, the wet etch rate is very low relative to RIE, leading to process times that are longer than desired.
RIE process times are relatively shorter than wet etch processes, but there are several problems with RIE-based methods. First, it is difficult to etch the dielectric spacer selective to p-doped and more importantly, n-doped Si in the extension and S/D regions of the semiconductor device. This lack of specificity can lead to severe negative device performance. Specifically, a method with poor selectivity to doped Si can produce the undesired structure shown schematically in FIGS. 1(a)-1(c).
As shown, FIG. 1(a) depicts a cross-sectional view of a portion of a semiconductor device manufactured in accordance with conventional prior art processing techniques. In FIG. 1(a), a semiconductor device 10 includes a substrate 12 and a patterned gate stack 15 including gate silicide contact 18 formed thereon. Each patterned gate stack 15 comprises a gate material such as polycrystalline silicon, as is conventionally known. The patterned gate stack 15 is formed on a thin gate dielectric layer (not shown) previously formed on top of the substrate 12. Prior to the implantation of the silicon in the extension and S/D regions of the device 12, a thin nitride spacer 20 is first formed on sidewalls of patterned gate stack 15. The silicon in the S/D regions of the device are then reacted with metal to form low resistivity cobalt, titanium, or nickel silicide contacts 18. FIG. 1(b) represents the structure during spacer removal by RIE. Here the RIE process has progressed to a point in which the nitride spacer 20 has been partially removed. FIG. 1(c) represents the semiconductor device 10 at the conclusion of the RIE process, after the spacer 20 has been removed. As shown, the Si extension regions 22 are recessed by plasma damage during the RIE process. This leads to a loss of electrical contact between the gate and the S/D. Furthermore, it is difficult to remove densified silicon nitride selective to metal silicide. Damage to the silicide used to contact the gate and S/D can lead to higher contact resistance or even electrical shorts. Additionally, it is difficult to remove densified silicon nitride selective to oxide. This is especially problematic because oxide is often used as a composite spacer material and oxide is used for fill in shallow trench isolation.
Hence, a method for removing dielectric spacers in a semiconductor device with a high selectivity to doped Si, metal silicide and oxide is needed to produce the desired structure having substantially no recesses in the semiconductor substrate over the extension or S/D regions.